← back to hub

pipeline & hazards

1. The 5-Stage Pipeline

Every single instruction must go through 5 hardware stages.

  • Fetch (IF): Grab the instruction from RAM.
  • Decode (ID): Figure out what it means and check registers.
  • Execute (EX): The ALU does the math.
  • Memory (MEM): Read/Write to data RAM if necessary.
  • Writeback (WB): Save the result back to a CPU Register.

2. Data Hazards & The Stall Condition

The exact logic that forces a CPU to freeze.

  • If I1 is writing to R1, it "Locks" that register.
  • When I2 enters the Decode stage, it checks the lock table. The Condition: If I2 needs to read a register that is currently locked by a previous instruction, it must wait.
  • The Decode stage hits the brakes and STALLS the pipeline.

3. The Pipeline Bubble

What happens when the pipeline stalls?

  • To keep the hardware moving, the Decode stage injects a Bubble (No-Op) into the Execute stage. This is a completely wasted clock cycle!
  • Watch the Hazard Log below to see exactly which register caused the stall in real-time.
Hardware Configuration:
Fetch
Decode
Execute
Memory
Writeback
Bubble (Stall)
Performance Metrics
Clock Cycles: 0
Instructions Finished: 0
Wasted Bubbles: 0
0.00
Instructions Per Cycle (IPC)
Live Register File
Instruction Queue
Hazard Detection Unit