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cache & bus

1. The Memory Wall

CPUs are mathematically starving for data.

  • A modern CPU can execute an instruction in 1 clock cycle.
  • Fetching data from physical RAM takes about 200 clock cycles because the signal has to leave the CPU chip, travel across the motherboard via the System Bus, and find the data in the RAM sticks.
  • If the CPU always read from RAM, it would spend 99% of its time frozen.

2. The Cache Hierarchy

To fix this, we glue tiny amounts of ultra-fast memory directly onto the CPU chip.

  • L1 Cache: Extremely tiny (e.g., 32KB), but blazing fast (1 cycle cost). Private to each core.
  • L2 Cache: Slightly larger (e.g., 512KB), slightly slower (10 cycles).
  • L3 Cache: Large (e.g., 32MB), slower (40 cycles). Shared among all cores.

3. Hits, Misses, and AMAT

The OS constantly tries to guess what data you need next and moves it into L1.

  • Cache Hit: The data is found! (Fast).
  • Cache Miss: The data isn't there. The CPU stalls and searches the next level down.
  • AMAT (Average Memory Access Time): The ultimate metric. By having a 90% Hit Rate in L1, the *average* cost to fetch data drops from 200 cycles down to roughly 2 or 3 cycles!
CPU Core
Executing Instructions
0 Hits
L1 Cache
Cost: 1 Cycle | Size: 32 KB
0 Hits
L2 Cache
Cost: 10 Cycles | Size: 512 KB
0 Hits
L3 Cache (Shared)
Cost: 40 Cycles | Size: 32 MB
0 Accesses
Main Memory (RAM)
Cost: 200 Cycles | Size: 16 GB
Total Data Requests: 0
Total Cycles Spent: 0
0.0
Average Memory Access Time (Cycles)
Memory Management Unit (MMU) Log